There has been an increasing demand for higher power and a higher withstand voltage in lead frames and semiconductor devices of the prior art, e.g., power semiconductor devices in which power semiconductor elements such as a MOS-FET and an IGBT are mounted. Thus in some semiconductor elements and packages for the semiconductor elements in response to the demand, an electrical resistance at the joint of the semiconductor element and an external terminal is reduced by a strip of Al (aluminum ribbon) to apply a large current with a low resistance. In order to further reduce a resistance and improve connection stability, however, multiple Al ribbons are connected in a stacked manner with an increased cross sectional area.
FIGS. 3(a) to 3(c) show the configuration of a semiconductor device of the prior art. The semiconductor device is a power semiconductor device. FIG. 3(a) is a plan view showing the configuration of the semiconductor device of the prior art. FIG. 3(b) is a sectional view showing the configuration of the semiconductor device of the prior art, taken along line Y-Y′ of FIG. 3(a). FIG. 3(c) is a plan view showing the main part of the semiconductor device in which the surface of a lead frame is plated according to the prior art.
In FIGS. 3(a) and 3(b), a power semiconductor device 101 has a semiconductor element 103 mounted on the die pad of a lead frame 102. A drain terminal 102a formed on the surface of the die pad and a drain electrode 103c of the semiconductor element 103 are bonded to each other.
On the surface of the semiconductor element 103, a source electrode 103a and a gate electrode 103b are formed. Further, the drain electrode 103c is formed on the back side of the semiconductor element 103.
Provided on the source electrode 103a is a relatively thin conductive ribbon 105. The conductive ribbon 105 is bonded to the source electrode 103a by ultrasonic bonding. On the conductive ribbon 105, a conductive ribbon 106 is provided that is larger in thickness than the conductive ribbon 105. The source electrode 103a and the conductive ribbon 106 are bonded by ultrasonic bonding with the conductive ribbon 105 interposed between the source electrode 103a and the conductive ribbon 106, so that a joint 108 is formed.
The other side of the conductive ribbon 106 is similarly bonded by ultrasonic bonding with the conductive ribbon 105 interposed between the conductive ribbon 106 and a source terminal 102b of the lead frame 102, so that a joint 108 is formed. By using the conductive ribbon 106 thus, a bonded area is increased and an electric resistance at the joint is reduced, so that a large current can be passed.
Further, the gate electrode 103b and a gate terminal 102c of the lead frame 102 are connected to each other via a conductive wire 109. This is because a large current does not pass between the gate electrode 103b and the gate terminal 102c. A wire bonding technique for, e.g., a gold wire is used according to the prior art.
The lead frame 102, the semiconductor element 103, the conductive ribbons 105 and 106, and the conductive wire 109 are resin molded with molding resin 112 to form the power semiconductor device 101 (e.g., see patent document 1).
In another semiconductor device of the prior art, when a semiconductor element is mounted on a lead frame via lead-free solder, the mounting region is partially plated with a precious metal to improve the reliability of mounting (e.g., see patent document 2).
In the prior art configuration of patent document 1, the relatively thin conductive ribbons 105 are first bonded and then the conductive ribbon 106 larger in thickness than the conductive ribbons 105 is bonded thereon by ultrasonic bonding. Thus it is possible to apply a larger pressure and ultrasonic power, so that the conductive ribbon 106 can be bonded with a cross sectional area large enough to reduce a bonding resistance. However, the semiconductor element 103 receives a stress at least twice because of heat and vibrations during ultrasonic bonding, so that the semiconductor element 103 disadvantageously becomes less reliable. Moreover, the use of different kinds of conductive ribbons results in a complicated ultrasonic bonding process and a complicated device and equipment, disadvantageously increasing the production cost.
In the prior art configuration of patent document 2, in order to improve the reliability of connection between different kinds of conductive bonding materials and the electrode of a semiconductor element and the lead terminal of a lead frame, the bonded region of the lead terminal may be partially plated depending upon the conductive bonding material.
Thus as shown in FIG. 3(c), a second coating 111 highly bondable to the conductive wire 109 is applied to a region bonded to the conductive wire 109 on the lead frame 102, and a first coating 110 highly bondable to the conductive ribbon 106 is applied to a region serving as the joint 108 bonded to the conductive ribbon 106 on the lead frame 102. The highly bondable coatings are applied to the terminals serving as the joints depending upon the conductive bonding materials, so that the bonding of the joints can be improved and a bonding resistance can be reduced. Thus a resistance can be sufficiently reduced without bonding at a single point several times.